(a) Field of the Invention
The present invention relates to a thin film transistor array substrate. More particularly, the present invention relates to a thin film transistor array substrate, a method for manufacturing the same and a system for inspecting the substrate.
(b) Description of the Related Art
Liquid crystal displays are at present the most commonly used flat panel display. The liquid crystal display (LCD) is structured having liquid crystal material injected between two substrates. Voltages of different potentials are applied to electrodes of the substrates to form electric fields such that the alignment of liquid crystal molecules of the liquid crystal material is varied. Accordingly, the transmittance of incident light is controlled to enable the display of images.
Formed on one of the substrates is wiring, which transmits image signals and scanning signals. The wiring defines pixels in a matrix arrangement, and each pixel is electrically connected to the wiring. Formed on the same substrate as the wiring are thin film transistors (TFTs) for discontinuing the transmittance of the image signals, and pixel electrodes for transmitting the image signals. This substrate is referred to as a TFT substrate.
Pads are connected to ends of the wiring. The pads are used as a means to transmit the scanning signals and image signals to the wiring from an external drive circuit. To prevent damage to the pads, it is preferable to cover the pads with auxiliary pads made of a conducting material in another layer.
However, a space between the pads decreases as the resolution of the LCD increases. Thus, contact defects of a probe pin used in inspecting the liquid crystal panel increases contact resistance of the pads. This is particularly true when IZO (indium zinc oxide), which has a high surface contact resistance, is used for the auxiliary pads, making it unable to inspect the liquid crystal panel.
The present invention has been made in an effort to solve the above problems.
It is an object of the present invention to provide a thin film transistor array substrate, a method for manufacturing the same, and a system for inspecting the substrate that lowers a contact resistance with a probe pin.
To achieve the above object, the present invention provides a thin film transistor substrate comprising gate wiring formed on an insulation substrate and including gate lines, and gate electrodes and gate pads connected to the gate lines; a gate insulation layer covering the gate wiring; a semiconductor layer formed over the gate insulation layer; data wiring formed over the gate insulation layer and including data pads; a protection layer covering the data wiring; auxiliary pads connected to the data pads through contact holes formed in the protection layer; and a pad auxiliary layer formed protruding a predetermined height under the data pads.
According to a feature of the present invention, the pad auxiliary layer is formed on a same layer as the semiconductor layer.
According to another feature of the present invention, the pad auxiliary layer is formed on a same layer as the gate wiring.
According to yet another feature of the present invention, the data wiring further includes data lines, source electrodes connected to the data lines, and drain electrodes provided opposing the source electrodes with respect to the gate electrodes.
According to still yet another feature of the present invention, the substrate further comprises pixel electrodes formed on a same layer as the auxiliary pads and connected to the drain electrodes.
According to still yet another feature of the present invention, the substrate further comprises an ohmic contact layer formed between the semiconductor layer and the data wiring, the ohmic contact layer being doped with impurities at a high concentration.
According to still yet another feature of the present invention, the ohmic contact layer is formed in the same shape as the data wiring.
According to still yet another feature of the present invention, the semiconductor layer, except for a channel formed between the source electrodes and the drain electrodes, is formed in the same shape as the data wiring.
According to still yet another feature of the present invention, the pad auxiliary layer is made of an aluminum group conducting material, the auxiliary pads are made of IZO, and the pad auxiliary layer and the auxiliary pads are interconnected via the contact holes of the data pads.
In another aspect, the present invention provides a thin film transistor comprising gate wiring formed on an insulation substrate and including gate lines, and gate electrodes and gate pads connected to the gate lines; a gate insulation layer covering the gate wiring; a semiconductor layer formed over the gate insulation layer; data wiring formed over the gate insulation layer and including data lines, source electrodes connected to the data lines, drain electrodes provided opposing the source electrodes with respect to the gate electrodes, and data pads connected to the data lines; a protection layer covering the data wiring; and pixel electrodes connected to the drain electrodes through contact holes formed on the protection layer, wherein the protection layer or the gate insulation layer is removed at pad portions where the data pads are formed such that at least the data pads are fully exposed.
According to a feature of the present invention, the thin film transistor further comprises auxiliary pads formed on a same layer as the pixel electrodes and covering the data pads.
The inspection system for determining whether a thin film transistor substrate is defective, in which the thin film transistor substrate comprises gate wiring including gate lines, gate electrodes and gate pads, and data wiring including source electrodes and drain electrodes, includes a probe pin for contacting the gate pads or data pads and transmitting a corresponding signal, wherein a contact tip at a distal end of the probe pin for contacting the gate pads or the data pads is rounded, and a radius of the rounded contact tip is 2 xcexcm or less, or the rounded contact tip is coated with gold (Au).